MARSS-RISCV: TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

Contents:

• 1. In-Order Core Microarchitecture
  • 1.1. Overview of Pipeline Stages
• 2. Out-of-Order Core Microarchitecture
  • 2.1. Overview of Pipeline Stages
  • 2.2. Stage-wise activities based on the instruction type
• 3. Branch Prediction Unit
  • 3.1. Branch Target Buffer
  • 3.2. Return Address Stack
  • 3.3. Two-Level Adaptive Predictor
  • 3.4. Interaction with the CPU Pipeline
  • 3.5. Timings
• 4. Simulation of memory access delay
  • 4.1. Translation look-aside buffers (TLB)
  • 4.2. Caches
  • 4.3. Memory controller
  • 4.4. DRAM
• 5. Simulating Benchmarks
  • 5.1. System Requirements and Dependencies
  • 5.2. Compiling the simulator
  • 5.3. Preparing the bootloader, kernel, and userland image
  • 5.4. Configuring the Simulator
  • 5.5. Run the simulator
  • 5.6. Load the benchmark and the simulation utility programs inside the guest VM
  • 5.7. Run Benchmark